1. Field of the Invention
The present invention relates to semiconductor memory devices having an internal voltage generation circuit and thin film transistors used therein and, more particularly, to a semiconductor memory device with reduced power consumption and a thin film transistor for achieving reduction in power consumption of a semiconductor memory device.
2. Description of the Background Art
A conventional internal voltage generation circuit which can be used in a Static Random Access Memory (hereinafter referred to as "SRAM") is disclosed, for example, Japanese Patent Laying-Open No. 3-207091. The conventional internal voltage generation circuit will be described below.
FIG. 23 is a circuit diagram showing in detail a portion of an SRAM having the conventional internal voltage generation circuit.
Referring to FIG. 23, the SRAM with the conventional internal voltage generation circuit includes an internal circuit 1 and a voltage-down circuit 57 as an internal voltage generation circuit. Voltage-down circuit 57 includes resistors R1, R2 and R3, PMOS transistors QP1 and QP2, and an NMOS transistor QN.
Resistors R1 and R2 are connected in series between a node having an external power supply voltage Vcc and a node having a ground voltage. PMOS transistor QP1 and resistor R3 are connected in series between a node having external power supply voltage Vcc and a node having the ground voltage. The gate of PMOS transistor QP1 and a node N1 are connected.
PMOS transistor QP2 is connected between a node with external power supply voltage Vcc and a node N3. PMOS transistor QP2 has a gate connected to a node N2. NMOS transistor QN is connected between a node with external power supply voltage Vcc and node N3. NMOS transistor QN has a gate connected to a node with external power supply voltage Vcc. Node N3 is connected to internal circuit 1.
Here, internal circuit 1 is such circuit as a memory circuit. Description will now be made of operation of voltage-down circuit 57.
When external power supply voltage Vcc is a low voltage of, for example, 3 V, PMOS transistor QP1 is turned off by the voltage of node N1 determined by the ratio of the resistance of resistor R1 to that of resistor R2. Node N2 has a voltage reduced to approximately 0 V by resistor R3. As a result, PMOS transistor QP2 is turned on and node N3 receives external power supply voltage Vcc of 3 V. Thus, external power supply voltage Vcc of 3 V is supplied to internal circuit 1.
In contrast, when external power supply voltage Vcc is increased to a high voltage of, for example, 5 V exceeding a predetermined voltage, PMOS transistor QP1 is turned on by the voltage of node N1. The voltage of node N2 is increased to external power supply voltage Vcc, thereby turning off PMOS transistor QP2. As a result, the voltage (current) to be applied to internal circuit 1 is all conveyed through NMOS transistor QN. Thus, internal circuit 1 receives a voltage of approximately 3.5 V obtained by reducing external power supply voltage Vcc of 5 V by a threshold voltage Vtn of NMOS transistor QN.
Thus, when external power supply voltage Vcc exceeds a predetermined voltage, a voltage is applied by NMOS transistor QN, thereby preventing application of a high voltage to internal circuit 1 to secure reliability. In addition, when external power supply voltage Vcc is decreased to a voltage lower than a predetermined voltage, a voltage is applied mainly by PMOS transistor QP2 to avoid loss of data in the memory circuit (memory cell) as internal circuit 1.
As described above, conventional voltage-down circuit 57 is capable of retaining data at a lOW voltdge and reducing a high voltage. Here, the value of the predetermined voltage (hereinafter referred to as "switching point") as a condition for turning off PMOS transistor QP2 (turning on PMOS transistor QP1) is determined mainly by the ratio of the resistance of resistor R1 to that of resistor R2.
More specifically, the condition for switching direct application of external power supply voltage Vcc to internal circuit 1 by PMOS transistor QP2 and application of the external power supply voltage Vcc which is reduced by threshold voltage Vtn to internal circuit 1 by the diode-connected NMOS transistor QN is determined mainly by the ratio of the resistance of resistor R1 to that of R2.
Resistors R1, R2 and R3 are resistance elements with high resistance which are formed of polysilicon.
As described above, conventional voltage-down circuit 57 employs one resistance element as resistor R1. The same applies to resistors R2 and R3. Therefore, in a process of fabricating resistors R1 and R2, the actual resistance value may be different from the designed resistance value due to displacement of the mask and other factors, whereby the above-described switching point cannot be determined as designed.
Furthermore, if resistance values of resistors R1-R3 are increased for reduction in consumed current in conventional voltage-down circuit 57, the response speed of voltage-down circuit 57 to external power supply voltage Vcc (the speed at which the voltage of node N1 changes in response to a change in external power supply voltage Vcc) is decreased, thereby causing malfunction of voltage-down circuit 57.
More specifically, PMOS transistor QP2 may not be turned off (PMOS transistor QP1 may not be turned on) even if external power supply voltage Vcc exceeds the above-described switching point (predetermined voltage), and PMOS transistor QP2 may not be turned on (PMOS transistor QP1 may not be turned off) even if external power supply voltage Vcc falls below the above-described switching point (predetermined voltage).
Especially, when external power supply voltage Vcc greatly changes during, for example, power-on, an abnormal ordinary voltage may be applied to internal circuit 1 because of slow response of voltage-down circuit 57 to external power supply voltage Vcc. More specifically, since voltage-down circuit 57 responds slowly to external power supply voltage Vcc, PMOS transistor QP2 is not turned off (PMOS transistor QP1 is not turned on) even when external power supply voltage Vcc exceeds the above-described switching point (predetermined voltage). As a result, external power supply voltage Vcc which is a high voltage exceeding the above-described switching point is undesirably applied to internal circuit 1.